Xilinx Virtex-6 FPGA

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 27
UG366 (v2.5) January 17, 2011
Port and Attribute Summary
Ports:
• TXDLYALIGNDISABLE
• TXDLYALIGNMONENB
• TXDLYALIGNMONITOR[7:0]
• TXDLYALIGNOVERRIDE
• TXDLYALIGNRESET
• TXDLYALIGNUPDSW
• TXENPMAPHASEALIGN
• TXOUTCLK
• TXPLLLKDET
• TXPLLLKDETEN
• TXPMASETPHASE
• TXUSRCLK
page 155
page 155
page 155
page 155
page 155
page 155
page 156
page 156
page 156
page 156
page 156
page 156
Attributes:
• TX_BUFFER_USE
• TX_BYTECLK_CFG[5:0]
• TX_DATA_WIDTH
• TX_DLYALIGN_CTRINC
• TX_DLYALIGN_LPFINC
• TX_DLYALIGN_MONSEL
• TX_DLYALIGN_OVRDSETTING
• TX_PMADATA_OPT
• TX_XCLK_SEL
• TXOUTCLK_CTRL
page 157
page 157
page 157
page 157
page 157
page 157
page 157
page 157
page 158
page 158
TX Pattern Generator
Ports:
• TXENPRBSTST[2:0]
• TXPRBSFORCEERR
page 164
page 164
Attributes:
• RXPRBSERR_LOOPBACK
page 164
TX Oversampling
Attributes:
• TX_OVERSAMPLE_MODE
page 166
TX Polarity Control
Ports:
• TXPOLARITY
page 166
TX Fabric Clock Output Control
Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
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