Xilinx Virtex-6 FPGA User Manual

26 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
TX Initialization
Ports:
• GTXTEST[12:0]
• GTXTXRESET
• PLLTXRESET
• TSTIN[19:0]
• TXDLYALIGNRESET
• TXRESET
• TXRESETDONE
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Attributes:
• TX_EN_RATE_RESET_BUF
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TX Encoder
Ports:
• TXBYPASS8B10B[3:0]
• TXCHARDISPMODE[3:0]
• TXCHARDISPVAL[3:0]
• TXCHARISK[3:0]
• TXENC8B10BUSE
• TXKERR[3:0]
• TXRUNDISP[3:0]
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TX Gearbox
Ports:
• TXGEARBOXREADY
• TXHEADER[2:0]
• TXSEQUENCE[6:0]
• TXSTARTSEQ
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Attributes:
• GEARBOX_ENDEC
• TXGEARBOX_USE
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TX Buffer
Ports:
• TXBUFSTATUS[1:0]
• TXRESET
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Attributes:
• TX_BUFFER_USE
• TX_OVERSAMPLE_MODE
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TX Buffer Bypass
Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English