Xilinx Virtex-6 FPGA

26 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
TX Initialization
Ports:
• GTXTEST[12:0]
• GTXTXRESET
• PLLTXRESET
• TSTIN[19:0]
• TXDLYALIGNRESET
• TXRESET
• TXRESETDONE
page 138
page 138
page 138
page 138
page 138
page 138
page 138
Attributes:
• TX_EN_RATE_RESET_BUF
page 138
TX Encoder
Ports:
• TXBYPASS8B10B[3:0]
• TXCHARDISPMODE[3:0]
• TXCHARDISPVAL[3:0]
• TXCHARISK[3:0]
• TXENC8B10BUSE
• TXKERR[3:0]
• TXRUNDISP[3:0]
page 145
page 145
page 145
page 145
page 145
page 146
page 146
TX Gearbox
Ports:
• TXGEARBOXREADY
• TXHEADER[2:0]
• TXSEQUENCE[6:0]
• TXSTARTSEQ
page 147
page 147
page 147
page 147
Attributes:
• GEARBOX_ENDEC
• TXGEARBOX_USE
page 147
page 147
TX Buffer
Ports:
• TXBUFSTATUS[1:0]
• TXRESET
page 154
page 154
Attributes:
• TX_BUFFER_USE
• TX_OVERSAMPLE_MODE
page 154
page 154
TX Buffer Bypass
Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
www.BDTIC.com/XILINX