Xilinx Virtex-6 FPGA

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 25
UG366 (v2.5) January 17, 2011
Port and Attribute Summary
Attributes:
• BGTEST_CFG
• BIAS_CFG
• PMA_TX_CFG
• POWER_SAVE
• TRANS_TIME_FROM_P2
• TRANS_TIME_NON_P2
• TRANS_TIME_RATE
• TRANS_TIME_TO_P2
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Loopback
Ports:
• LOOPBACK[2:0]
Attributes:
• TXDRIVE_LOOPBACK_HIZ
• TXDRIVE_LOOPBACK_PD
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page 125
DRP
Ports:
• DADDR[7:0]
• DCLK
• DEN
• DI[15:0]
• DRPDO[15:0]
• DRDY
• DWE
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FPGA TX Interface
Ports:
• MGTREFCLKFAB[1:0]
• TXCHARDISPMODE[3:0]
• TXCHARDISPVAL[3:0]
• TXDATA[31:0]
• TXUSRCLK
• TXUSRCLK2
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Attributes:
• GEN_TXUSRCLK
• TX_DATA_WIDTH
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Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
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