Xilinx Virtex-6 FPGA

24 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Chapter 1: Transceiver and Tool Overview
PLL
Ports:
• PLLTXRESET
• PLLRXRESET
• TXPLLLKDET
• RXPLLLKDET
• TXPLLLKDETEN
• RXPLLLKDETEN
• TXPLLPOWERDOWN
• RXPLLPOWERDOWN
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Attributes:
• PMA_CFG
• TX_CLK_SOURCE
• TX_TDCC_CFG
• TXPLL_COM_CFG
• RXPLL_COM_CFG
• TXPLL_CP_CFG
• RXPLL_CP_CFG
• TXPLL_DIVSEL_FB
• RXPLL_DIVSEL_FB
• TXPLL_DIVSEL_OUT
• RXPLL_DIVSEL_OUT
• TXPLL_DIVSEL_REF
• RXPLL_DIVSEL_REF
• TXPLL_DIVSEL45_FB
• RXPLL_DIVSEL45_FB
• TXPLL_LKDET_CFG
• RXPLL_LKDET_CFG
• TXPLL_SATA
• RX_CLK25_DIVIDER
• TX_CLK25_DIVIDER
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Power Down
Ports:
• RXPLLPOWERDOWN
• RXPOWERDOWN[1:0]
• TXPDOWNASYNCH
• TXPLLPOWERDOWN
• TXPOWERDOWN[1:0]
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Table 1-1: Port and Attribute Summary (Cont’d)
Port/Attribute Section, Page
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