Xilinx Virtex-6 FPGA

304 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Appendix B: DRP Address Map of the GTX Transceiver
6h
15:13
R/W
RX_LOS_INVALID_INCR 2:0
1 000
2 001
4 010
8 011
16 100
32 101
64 110
128 111
12:10 RX_LOS_THRESHOLD 2:0
4
000
8 001
16 010
32 011
64 100
128 101
256 110
512 111
9:0 CHAN_BOND_SEQ_1_3 9:0 0-1023 1
(1)
7h
15:12
R/W
RX_IDLE_LO_CNT 3:0 0-15
1
(1)
11:10 CHAN_BOND_SEQ_LEN 1:0
1
00
2 01
Reserved
4
11
9:0 CHAN_BOND_SEQ_1_4 9:0 0-1023 1
(1)
8h
15
R/W
RX_EN_RATE_RESET_BUF
FALSE
0
TRUE 1
14 RX_EN_REALIGN_RESET_BUF
FALSE
0
TRUE 1
13:10 CHAN_BOND_SEQ_2_ENABLE 3:0 0-15 1
(1)
9:0 CHAN_BOND_SEQ_2_1 9:0 0-1023 1
(1)
9h
15
R/W
RX_EN_MODE_RESET_BUF
FALSE
0
TRUE 1
14 CHAN_BOND_KEEP_ALIGN
FALSE
0
TRUE 1
13:10 CHAN_BOND_2_MAX_SKEW 3:0 1-14 1
(1)
9:0 CHAN_BOND_SEQ_2_2 9:0 0-1023 1
(1)
Ah
15
R/W
RX_EN_IDLE_RESET_PH
FALSE
0
TRUE 1
14 CHAN_BOND_SEQ_2_USE
FALSE
0
TRUE 1
13:10 CHAN_BOND_SEQ_2_CFG 3:0 <4:0> 0-31 1
(1)
9:0 CHAN_BOND_SEQ_2_3 9:0 0-1023 1
(1)
Table B-1: Attributes DRP Address Map (Cont’d)
DADDR
DRP Bits R/W Attribute Name Attribute Bits Attribute Encoding
DRP Binary
Encoding
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