Name: Xilinx Virtex-6 FPGA
Brand: Xilinx
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Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 31

UG366 (v2.5) January 17, 2011

Port and Attribute Summary

Attributes:

• CDR_PH_ADJ_TIME

• PMA_CDR_SCAN

• PMA_RX_CFG

• RX_EN_IDLE_HOLD_CDR

• RX_EN_IDLE_RESET_FR

• RX_EN_IDLE_RESET_PH

• RX_EYE_SCANMODE

• RXPLL_DIVSEL_OUT

page 205

page 206

RX Clock Divider Control

Ports:

• MGTREFCLKFAB[1]

• O

• ODIV2

• PHYSTATUS

• RXRATE[1:0]

• RXRATEDONE

• RXRECCLK

• RXRECCLKPCS

page 209

Attributes:

• RX_EN_RATE_RESET_BUF

• RXPLL_DIVSEL_OUT

• RXRECCLK_CTRL

• TRANS_TIME_RATE

page 209

page 210

RX Margin Analysis

Ports:

• RXDATA[31:0]

page 212

Attributes:

• RX_EYE_OFFSET

• RX_EYE_SCANMODE

page 213

RX Polarity Control

Ports:

• RXPOLARITY

page 213

RX Oversampling

Ports:

• RXENSAMPLEALIGN

• RXOVERSAMPLEERR

page 215

Attributes:

• PMA_RX_CFG

• RX_OVERSAMPLE_MODE

page 215

Table 1-1: Port and Attribute Summary (Cont’d)

Port/Attribute Section, Page

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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English

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