Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 313
UG366 (v2.5) January 17, 2011
3Eh
15:10
R/W
Reserved 5:0
9:5 TX_DEEMPH_1 4:0 0-31
1
(1)
4:0 TX_DEEMPH_0 4:0 0-31 1
(1)
3Fh
15:8
R/W
Reserved 7:0
7:0 TRANS_TIME_RATE 7:0
40h
15:0 R/W Reserved 15:0
41h
31:16
R/W
TST_ATTR 31:16
42h
15:0 TST_ATTR 15:0
43h
15:6
R/W
Reserved 9:0
5:3 RXRECCLK_CTRL 2:0
RXRECCLKPCS
000
OFF_HIGH 110
OFF_LOW 101
RXPLLREFCLK_DIV1 011
RXPLLREFCLK_DIV2 100
RXRECCLKPMA_DIV1 001
RXRECCLKPMA_DIV2 010
2:0 TXOUTCLK_CTRL 2:0
TXOUTCLKPCS
000
OFF_HIGH 110
OFF_LOW 101
TXOUTCLKPMA_DIV1 001
TXOUTCLKPMA_DIV2 010
TXPLLREFCLK_DIV1 011
TXPLLREFCLK_DIV2 100
44h
15:10
R/W
Reserved 5:0
9:0 POWER_SAVE 9:0 0-1023
1
(1)
45h
15:12
R/W
Reserved 3:0
11:6 TX_USRCLK_CFG 5:0
5:0 TX_BYTECLK_CFG 5:0
46h
15:10
R/W
Reserved 5:0
9:0 RXRECCLK_DLY 9:0 0-1023
1
(1)
47h
15:10
R/W
Reserved 5:0
9:0
Reserved
9:0
48h
15:0 R/W Reserved 15:0
49h
15:0 R/W Reserved 15:0
4Ah
15:0 R/W Reserved 15:0
4Bh
15
R/W
Reserved
14 RX_EN_REALIGN_RESET_BUF2
FALSE
0
TRUE 1
13:11 Reserved 2:0
10:6 RX_DLYALIGN_EDGESET 4:0 0-31
1
(1)
5:3 TX_DLYALIGN_MONSEL 2:0 0-7 1
(1)
2:0 RX_DLYALIGN_MONSEL 2:0 0-7 1
(1)
Table B-1: Attributes DRP Address Map (Cont’d)
DADDR
DRP Bits R/W Attribute Name Attribute Bits Attribute Encoding
DRP Binary
Encoding
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English