Xilinx Virtex-6 FPGA

312 www.xilinx.com Virtex-6 FPGA GTX Transceivers User Guide
UG366 (v2.5) January 17, 2011
Appendix B: DRP Address Map of the GTX Transceiver
30h
15:14
R/W
Reserved 1:0
13:11 TX_IDLE_DEASSERT_DELAY 2:0 0-7
1
(1)
10 MCOMMA_DETECT
FALSE
0
TRUE 1
9:0 MCOMMA_10B_VALUE 9:0 0-1023 1
(1)
31h
15
R/W
GEN_TXUSRCLK
FALSE
0
TRUE 1
14:12 TX_DATA_WIDTH 2:0
20
011
8 000
10 001
16 010
32 100
40 101
11 TX_BUFFER_USE
FALSE
0
TRUE 1
10 PCOMMA_DETECT
FALSE
0
TRUE 1
9:0 PCOMMA_10B_VALUE 9:0 0-1023 1
(1)
32h
15:0 R/W PMA_CFG 15:0
33h
15:0 R/W PMA_CFG 31:16
34h
15:0 R/W PMA_CFG 47:32
35h
15:0 R/W PMA_CFG 63:48
36h
15:4
R/W
PMA_CFG 75:64
3:0 PMA_TX_CFG 19:16
37h
15:0 R/W PMA_TX_CFG 15:0
38h
15:14
R/W
Reserved 1:0
13:7 TX_MARGIN_FULL_0 6:0 0-127
1
(1)
6:0 TX_MARGIN_LOW_0 6:0 0-127 1
(1)
39h
15:14
R/W
TX_TDCC_CFG 1:0 0-3
1
(1)
13:7 TX_MARGIN_FULL_1 6:0 0-127 1
(1)
6:0 TX_MARGIN_LOW_1 6:0 0-127 1
(1)
3Ah
15
R/W
TXDRIVE_LOOPBACK_PD
FALSE
0
TRUE 1
14 TXDRIVE_LOOPBACK_HIZ
FALSE
0
TRUE 1
13:7 TX_MARGIN_FULL_2 6:0 0-127 1
(1)
6:0 TX_MARGIN_LOW_2 6:0 0-127 1
(1)
3Bh
15:14 Reserved 1:0
13:7 TX_MARGIN_FULL_3 6:0 0-127
1
(1)
6:0 TX_MARGIN_LOW_3 6:0 0-127 1
(1)
3Ch
15
R/W
TX_DRIVE_MODE
DIRECT
0
PIPE 1
14 Reserved
13:7 TX_MARGIN_FULL_4 6:0 0-127
1
(1)
6:0 TX_MARGIN_LOW_4 6:0 0-127 1
(1)
3Dh
15:0 R/W Reserved 15:0
Table B-1: Attributes DRP Address Map (Cont’d)
DADDR
DRP Bits R/W Attribute Name Attribute Bits Attribute Encoding
DRP Binary
Encoding
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