Xilinx Virtex-6 FPGA User Manual

Virtex-6 FPGA GTX Transceivers User Guide www.xilinx.com 311
UG366 (v2.5) January 17, 2011
27h
15
R/W
TX_EN_RATE_RESET_BUF
FALSE
0
TRUE 1
14:12 SATA_IDLE_VAL 2:0 0-7 1
(1)
11:6 SATA_MIN_INIT 5:0 1-61 1
(1)
5:0 SATA_MAX_INIT 5:0 1-61 1
(1)
28h
15
R/W
Reserved
14:12 SATA_BURST_VAL 2:0 0-7
1
(1)
11:6 SATA_MIN_BURST 5:0 1-61 1
(1)
5:0 SATA_MAX_BURST 5:0 1-61 1
(1)
29h
15:12
R/W
Reserved 3:0
11:6 SAS_MIN_COMSAS 5:0 1-61
1
(1)
5:0 SAS_MAX_COMSAS 5:0 1-61 1
(1)
2Ah
15:9
R/W
Reserved
6:0
8 RXPRBSERR_LOOPBACK 0-1
1
(1)
7:0 Reserved 7:0
2Bh
15:12
R/W
Reserved 3:0
11 RX_EN_IDLE_HOLD_DFE
FALSE
0
TRUE 1
10 RX_EN_IDLE_RESET_FR
FALSE
0
TRUE 1
9 RX_EN_IDLE_HOLD_CDR
FALSE
0
TRUE 1
8:0 Reserved 8:0
2Ch
15:0 R/W Reserved 15:0
2Dh
15:8
R/W
RX_EYE_OFFSET 7:0
7:0 DFE_CFG 7:0 0-255
1
(1)
2Eh
15:11
R/W
DFE_CAL_TIME 4:0 0-31
1
(1)
10:9 RX_EYE_SCANMODE 1:0 0-3 1
(1)
8RCV_TERM_VTTRX
FALSE
0
TRUE 1
7RCV_TERM_GND
FALSE
0
TRUE 1
6 TERMINATION_OVRD
FALSE
0
TRUE 1
5 Reserved
4:0 TERMINATION_CTRL 4:0 0-31
1
(1)
2Fh
15
R/W
TXGEARBOX_USE
FALSE
0
TRUE 1
14 TX_XCLK_SEL
TXUSR
1
TXOUT 0
13:11 TX_IDLE_ASSERT_DELAY 2:0 0-7 1
(1)
10 COMMA_DOUBLE
FALSE
0
TRUE 1
9:0 COMMA_10B_ENABLE 9:0 0-1023 1
(1)
Table B-1: Attributes DRP Address Map (Cont’d)
DADDR
DRP Bits R/W Attribute Name Attribute Bits Attribute Encoding
DRP Binary
Encoding
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Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English