AMD AMD5K86 - Bus Interface

18524B/0- Mar1996
AMD~
AMD5,136 Processor Technical Reference Manual
Bus Interface
This chapter describes two closely related subjects, bus signals
(Sections 5.1 and 5.2) and the bus-cycle protocols implemented
with those signals (Sections 5.3 and 5.4). These sections
describe only the architectural characteristics and functions of
the signals and bus cycles. The processor data sheet defines
the setup and hold times for signals.
Throughout this chapter, unless otherwise stated, the term
clock refers to bus-clock (eLK) cycles, not processor-clock
cycles. The term cycle refers to bus cycles not clock cycles. The
terms asserted and negated mean that a signal is sampled
asserted or sampled negated by its target on the signal's active
(typically rising) clock edge.
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