AMD AMD5K86 - L2 Cache; Cacheability and Cache-State Control

18524B/O-Mar1996
6.2.1
6.2.2
Cache
AMDl1
AMD5J<!36 Processor Technical Reference Manual
page table entries to control caching properties for specific
physical pages. The PCD and PWT bits control the state of the
PCD and PWT output signals, which system logic can use to
control L2 caching.
L2 Cache
To improve system performance, an L2 cache can be added
between the processor and main memory. The L2 cache can be
implemented for 3-2-2-2 bursts using lS-ns asynchronous
SRAM on a 60-MHz or 66-MHz bus. Faster bursts can be imple-
mented with synchronous SRAM. 9-ns SSRAM can achieve 3-1-
1-1
bursts at 66 MHz and 10-ns SSRAM can achieve 2-1-1-1
bursts at 50 MHz.
Most system designs that implement an L2 cache do so using
(a) an L2 cache that is significantly larger than the combined
sizes of the L1 caches, (b) L2 cache lines that are at least as
wide as L1 cache lines (32 bytes or more), and (c) cache-line
fills that follow the principle of inclusion, which says that any
line in the L1 cache is guaranteed to be in the L2 cache.
The first principle (L2 cache bigger) guarantees that the L2
cache will have data that is not already in the L1 cache. The
second principle (L2 cache line size greater or equal to L1
cache line size) can simplify and speed up transfers from the
L2 cache to the L1 cache. The third principle (inclusion) can
simplify and speed up cache-coherency signaling for inquire
cycles-if an inquire cycle misses in the L2 cache, the system
can safely assume it is not in the L1 cache without having to
query the processor directly.
Cacheability and Cache-State Control
The PCD bits maintained by the operating system are a deter-
mining factor in the state of the processor's CACHE output sig-
nal for each bus cycle. CAcHE indicates the processor's intent
to drive a read or write cycle as a burst cycle. The signal is only
asserted for reads that the operating system determines to be
cacheable, and for write backs of modified lines. These write-
backs can be caused by inquire cycles, internal snoops, the
FLUSH signal, the WBINVD instruction, or cache-line replace-
ments. CACHE is not asserted for cache hits that are
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