AMD AMD5K86 - TABLE 5-4. Address-Generation Sequence During Bursts

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18524B/O-Mar1996 AMD5JJ6 Processor Technical Reference Manual
5.2.2 All-Al (Address Bus)
Summary
Driven, Sampled, and
floated
Details
Signal Descriptions
All-AS Bidirectional, A4-Al Output
A31-A3 carries the physical address for the current bus cycle.
The processor drives addresses on A31-A3 during memory and
I/O cycles, and cycle definition information during special bus
cycles. It samples addresses on A31-AS during inquire cycles.
As Outputs: The processor drives A31-A3 from the clock in
which IDS is asserted until the last expected BRDY of the bus
cycle. The processor also drives A31-A3 without IDS during
cache accesses. A31-A3 are driven during memory cycles
(including cache writethroughs and writebacks), I/O cycles,
inquire cycle writebacks, locked cycles, special bus cycles, and
interrupt acknowledge operations in the normal operating
modes (Real, Protected, and Virtual-8086) and in SMM, and
while PRDY is asserted. During special bus cycles and inter-
rupt acknowledge operations, the address signals simply sup-
port bus cycle definition; they do not provide an address.
The processor floats A31-A3 as outputs, one clock after system
logic asserts AHOLD or BUFF, and in the same clock that the
processor asserts HLDA.
As Inputs: While AHOLD, BUFF, or HLDA is asserted, the pro-
cessor samples A31-AS in the same clock as EAUS. A31-A5 are
sampled in this way during inquire cycles in the normal operat-
ing modes (Real, Protected, and Virtual-8086) and in SMM,
including during the Shutdown, Halt, and Stop Grant states,
and while PRDY is asserted. The A4-A3 signals are not inter-
preted as part of the inquire cycle address but must neverthe-
less be driven at valid 0 or 1 logic levels. The processor may
again drive A31-A3 in the next clock after system logic negates
AHOLD, BUFF, or HOLD.
A31-A3 are never driven or sampled in the Stop Clock state, or
while RESET or INIT is asserted.
During processor-initiated bus cycles, the processor drives
A31-A3 with IDS to define an eight-byte (quadword) starting
address in physical memory or 1/0 space. System logic inter-
prets these addresses in conjunction with the BE7-BEU and
cycle definition (DiC, MIID, and W/R) outputs, and with the
:A2UM input. The processor drives BE7-BEU to define the valid-
ity of each of the eight bytes accessed by the quadword
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