AMD AMD5K86 - RDYC (Burst Ready)

AMD~
AMD5J!36 Processor Technical Reference Manual 1 8524B/O-Marl 996
5-44
The assertion of NA acts as an assertion of BRDY only when
the processor samples KEN or WBIWT.
The processor drives or asserts the following outputs relative
to the assertion of BRDY:
•
D63-DO-For single-transfer write cycles, the processor
drives data from one clock after ADS until BRDY is
returned. For burst transfers, the processor drives data
from one clock after ADS until the first BRDY is returned,
and thereafter from each BRDY until the next BRDY.
•
DP7-DPO-Same as D63-DO.
• PCHK-Two clocks after every BRDY for writes.
In addition to the above uses of BRDY on the 486 processor,
BRDY on the AMD5
K
86 and Pentium processors is used for
both single-transfer and burst cycles, and it terminates special
bus cycles.
Unlike BRDY on the 486 processor, BRDY on the AMD5
K
86
and Pentium processors is used for both single-transfer and
burst cycles, and it terminates special bus cycles. On the 486
processor, single-transfer cycles and special bus cycles use
RDY; BRDY is used only for burst cycles. The BLAST output
on the 486 processor is not implemented on the AMD5
K
86 and
Pentium processors, which instead use the CACHE output to
indicate cacheability. However, unlike the 486 processor,
which can terminate a burst cycle prematurely by negating
BLAST, the AMD5
K
86 and Pentium processors cannot termi-
nate a burst prematurely.
Bus Interface