AMD AMD5K86 - APCHK (Address Parity Check)

AMD~
AMD5J136 Processor Technical Reference Manual
185248/0- Mar1996
5.2.6 AP (Address Parity)
Bidiredional
Summary
Driven, Sampled, and
floated
Details
5-12
AP carries the even parity bit for cache line addresses driven
and sampled on A31-A5. The processor drives AP when it
drives an address for a read or write cycle. The processor sam-
ples AP during inquire cycles in order to drive the APCHK out-
put.
AP is driven, sampled, and floated with the same timing as
A31-A3. See the description of A31-A3 on page 5-2l.
The bit value driven on AP is counted with the bit values
driven on A31-A5 to determine address parity. If the total
number of 1 bits is even on AP and A31-A5, the address is con-
sidered free of error (thus the term even parity). If the total
number of 1 bits is odd, ~he address is considered to have an
error. The bit values driven on A4-A3 are not counted during
the parity checking.
In addition to generating and checking address parity, the pro-
cessor also generates and checks data parity using the DP7-
DPO and PCHK signals. See page 5-58 and 5-102 for details.
Unlike the handling of PCHK, however, the processor does not
capture the faulty address in a register when it asserts
APCHK. System logic must handle the error externally. Typi-
cal PC systems assert an interrupt signal such as NMI after a
parity error is detected.
Systems that do not implement address parity generation and
checking should tie AP either High or Low and ignore the
APcHK output.
Bus Interface