AMD AMD5K86 - Conditions for Driving and Sampling Signals

AMD~
185248/0- Mar1996
AMD5IJ6 Processor Technical Reference Manual
TABLE 5-1. Summary of Signal Characteristics (continued)
Signal
Type
Sampled (Input) or
Internal
Floated
3
Asserted (Output)2 Resistor
Every clock, in response to RIS. Asserted at
PRDY 0
instruction boundary after RIS is sampled
Low. Negated in the clock after RIS is sam-
pled High.
PWT
0
From ADS until last expected BRDY of the
RUFF +1 or
bus cycle.
HLDA
Every clock. Level-sensitive. Recognized at
RlSl
I next instruction boundary. Acknowledged
pullup
with PRDY.
RESETl I
Every clock. Recognized at next instruction
boundary.
SCYC
0
From ADS until last expected BRDY of the RUFF +1 or
bus cycle. HLDA
Every clock. Falling-edge-triggered. Recog-
SlVITl
I
nized at next instruction boundary.
pullup
Acknowledged with SMIACT.
From one clock after the last expected
BRDY of the bus cycle, while EWBE is
SMIACt 0
asserted, until the return from SMM inter-
rupt handler.
Every clock. Level-sensitive. Recognized at
STpCLKl
I
next instruction boundary. Acknowledged
pullup
with Stop Grant special bus cycle.
TCK
I
Always.
pullup
TDI I
Every rising TCK edge during the shiftJR
pullup
and shift_DR states.
While not in
TDO 0
Every falling TCK edge during the shiftJR shiftJR or
and shifcDR states.
shifcDR
state.
TMS
I
Every rising TCK edge.
pullup
TRST
I
Always sampled asynchronously.
pullup
Notes:
I.
Can be driven asynchronously or synchronously
2.
The term clock means bus clock (CLK). "+n" means n CLKs later.
3.
"+n" means n CLKs after the named signal is sampled active. All outputs and bidirectionals are floated during the float test (F[USR
at RESET).
Signal Overview
5-7