AMD AMD5K86 - TABLE 5-11. MESI-State Transitions for Inquire Cycles

AMD~
AMD5xB6 Processor Technical Reference Manual
18524B/O-Mar1996
5.2.25
Summary
Driven
Details
5-72
HIT (Inquire-Cycle Hit)
Output
The processor asserts HIT to indicate that an inquire cycle hit
a valid line in the processor's instruction or data cache.
The processor drives HIT every clock. The signal changes state
two clocks after the assertion of EADS and retains that state
until two clocks after the next EADS.
HIT is driven at all times, except while the processor is in the
Stop Clock state, or while RESET or INIT is asserted.
The processor asserts HIT if an inquire cycle address matches
the address of a valid line in the processor's instruction cache
in the shared state, or of a shared, exclusive, or modified line in
the processor's data cache (called a cache hit). The processor
holds HIT negated if the inquire cycle address does not match
any valid address in either cache (called a cache miss).
Table 5-11 shows the relationship between HIT, IIITM, and
INV. Inquire cycle logic in systems with look-aside caches can
be simplified by monitoring only IIITM and ignoring HIT. This
works because the resulting state of a hit line is determined
only by the state of the INV input during the assertion of
EADS:
• If INV is negated during a hit, the hit line-whether shared,
exclusive,
or modified-transitions to the shared state. Thus,
the inquiring master can safely cache the same data in the
shared state without knowing whether the inquire cycle hit
in the processor's cache (and thus, without system logic
monitoring HIT).
• If INV is asserted during a hit, the hit line-whether shared,
exclusive,
or modified-transitions to the invalid state. If the
line was modified before the inquire, IIITM is also asserted
and the line is written back before the invalidation; if the
line was shared or exclusive before the inquire, no writeback
occurs before the invalidation.
• If the inquire cycle misses, regardless of the state of INV,
the inquiring master can cache the target data in the shared
state, although it will not have enough information to cache
that line in the exclusive state (this requires that HIT be
monitored).
Bus Interface