AMD AMD5K86 - M;IO (Memory or I;O)

18524B/O-Mar1996
Signal Descriptions
AMD~
AMD5IJ6 Processor Technical Reference Manual
writeback is pending when BUFF is negated, the writeback
takes precedence over the restarting of the aborted cycles in
the locked operation.
For purposes of interrupts and exceptions, locked operations
are treated by the processor as if the entire multi-cycle opera-
tion were a single instruction. Thus, interrupts and exceptions
are not recognized during locked operations. The processor
samples BUSCHK if it is asserted with any BRDY of a locked
operation, but the processor does not generate an enabled
machine check interrupt for the BOSCHK until after the
locked operation completes, and thus the exception will not
intervene in the locked operation. If an edge-triggered inter-
rupt (FLO SR, sm, INIT, or NMI) is asserted during a locked
operation, the interrupt is latched and recognized after the
locked operation completes, even if the interrupt signal is not
held asserted until the locked operation completes.
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