AMD AMD5K86 - TABLE 5-18. MESI-State Transitions for Writes

18524B/O-Mar1996
AMD~
AMD5/J6 Processor Technical Reference Manual
the exclusive state, a subsequent write hit to the same line tran-
sitions the line to the modified state. During write hits, the
states of PWT and WBIWT can only change a line from shared
to exclusive; it cannot change an exclusive line to a shared line.
TABLE 5-17. MESI-State Transitions for Reads
Result of Cache Lookup
Signal or Event
Read Hit
Read Miss
shared exclusive modified
CACHE,PCD!
1
0
0 0
KEN
-
1 0 0 0
- -
-
PWT
-
-
1
-
0
- -
-
WBIWT
- - -
0 1
- -
-
Cache-Line Fill
(32 bytes)
no no yes
yes yes
no no no
State After Read
2
- -
shared shared exclusive
shared exclusive
modified
Notes:
- Don't care or not applicable.
1.
The PCD bit is one determinant of the state of rACRE.
2.
Transition occurs after any line fill. Lines in shared MESI state are said to be in writethrough state. Those in exclusive or modified
MESI states are said to be in writeback state.
Signal Descriptions S-IlS