AMD AMD5K86 - Built-In Self Test (BIST)

AMD~
AMD5,!J6 Processor Technical Reference Manual 18524BjO-Mar1996
TABLE 7-1. Hardware Configuration Register (HWCR) Fields
Bit Mnemonic Description
Function
31-8
- -
reserved
Disables data cache.
7 DDC Disable Data Cache
o = enabled, 1 == disabled.
Disables instruction cache.
6 DIC Disable Instruction Cache
o = enabled, 1 = disabled.
5 DBP Disable Branch Prediction
Disables branch prediction.
J
o = enabled, 1 = disabled.
4
- -
reserved
Debug control bits:
000 Off (disable HWCR debug control).
001 Enable branch-tracing messages.
See Section 7.6 on page 7-17.
010 reserved
3-1
DC Debug Control
011
reserved
100 reserved
101 reserved
110 reserved
111 reserved
Disable Stopping
Disables stopping of internal processor
0 DSPC
Processor Clocks
clocks
in the Halt and Stop Grant states.
o = enabled, 1 = disabled.
Notes:
Documentation on the Hardware Debug Tool (HDT) is available from AMD under a nondisclosure agreement
7-4
Test and Debug