AMD AMD5K86 - ADS (Address Strobe)

AMD~
AMD5~6 Processor Technical Reference Manual
1 8524B/O-Marl 996
5-24
If an inquire cycle occurs while the processor is driving a
Branch-Trace Message special bus cycle, the branch address
information driven by the processor on A31-A3 can be over-
written by the inquiring bus master. In such cases, system logic
should latch A31-A3 when ADS is asserted (that is, before
asserting AHOLD, BUFF or HOLD).
At the falling edge of RESET, the states of BRDYC and BUs:
CHI{ control the drive strength on A21-A3 (not including A31-
A22). The drive strength is weak for all states of BRDYC and
BUSCHK except BRDYC and BUSCHK both Low (0), in which
case the drive strength is strong. The A31-A22 signals use the
weak drive strength at all times. See the data sheet for details.
Unlike the Pentium processor, pipelined address-data transac-
tions are not supported by the AMD5
K
86 processor. Thus, the
NA input has no effect on the processor's address bus. NA only
affects the sampling time for the KEN and WBIWT inputs.
Bus Interface