AMD AMD5K86 - SMM State-Save Area

AMD~
18524BjO-Mar1996
AMD5t1J6 Processor Technical Reference Manuf!1
TABLE 6-1. Initial State of Registers in SMM
Initial Contents
Register
Selector Base Attributes
Limit
CS 3000h
0003_0000h
16-bit, expand-up
4 Gbytes
(see Section 6.3.4)
DS
OOOOh OOOO_OOOOh
16-bit, expand-up 4 Gbytes
ES OOOOh
OOOO_OOOOh
16-bit, expand-up 4 Gbytes
FS
OOOOh
OOOO_OOOOh 16-bit, expand-up 4 Gbytes
GS OOOOh
OOOO_OOOOh
16-bit, expand-up 4 Gbytes
SS
OOOOh
OOOO_OOOOh 16-bit, expand-up
4 Gbytes
General-Purpose
Unmodified
EFLAGS
00OO_OOO2h
EIP
OOOO_BOOOh
CRO
Bits 0, 2, 3, 31 cleared (PE, EM, TS, PG). Others are unmodified.
CR4
OOOO_OOOOh
GDTR
Unmodified
LDTR
Unmodified
IDTR Unmodified
TR
Unmodified
DR7 Unmodified
DR6 Undefined
6.3.2 SMM State-Save Area
When the processor acknowledges an sm interrupt by assert-
ing SMlACT, it saves its state in the 512-byte SMM sta~e-save
area shown in Table 6-2. The save begins at the top of the SMM
memory area (SMM Base Address + FFFFh) and fills down to
SMM base address + FEOOh.
Table 6-2 shows the offsets in the SMM state-save area relative
to the SMM base address. The SMM service routine can alter
any of the read/write values in the state-save area. The con-
tents of any reserved locations in the state-save area are not
necessarily the same between the AMD5
K
86 processor and the
Pentium or 486 processors.
System Management Mode (SMM) 6-25