AMD AMD5K86 - PRDY (Probe Ready)

AMD~
18524B/O-Mar1996 AMD5~6 Processor Technical Reference Manual
5.2.41 PEN (Parity Enable)
Summary
Sampled
Details
Signal Descriptions
Input
System logic can assert PEN to enable cycle information latch-
ing and (optionally) machine check exception generation for
data bus parity errors during read cycles.
The processor samples PEN every BRDY during read cycles.
PEN is sampled for memory and 110 reads, locked reads, and
interrupt acknowledge operations in the normal operating
modes (Real, Protected, and Virtual-8086) and in SMM, or
while PRDY is asserted. PEN is not sampled during any type of
write cycles or special bus cycles; or during the Shutdown,
Halt, Stop Grant, or Stop Clock states; or while BUFF, HLDA,
RESET, or INIT is asserted. While AHOLD is asserted, PEN is
sampled only to complete a bus cycle already begun before the
assertion of AHOLD.
If PEN is asserted when a data parity error is reported on
PCHK, the processor latches the physical address and cycle
definition of the failed bus cycle in its 64-bit machine check
address register (MCAR) and its 64-bit machine check type
register (MCTR). These registers can be read with the RDMSR
instruction. See Section 3.3.5 on page 3-35 for details on this
instruction.
In addition to latching the cycle address and definition, the
processor also generates a machine check exception (12h) if
the MCE bit in CR4 is set to 1 while PEN is asserted. System
logic must then handle the error externally. Typical PC sys-
tems provide a mechanism for asserting NMI during a parity
error.
If PEN is negated, neither the address and cycle definition
latching nor the machine check exception generation occur.
The MCE bit in CR4 also enables the generation of a machine
check exception during bus cycle errors that are indicated on
the BUSCHK input. The machine check mechanism is not, how-
ever, used for address parity errors indicated on APCHK.
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