AMD AMD5K86 - TABLE 5-6. Encodings for Special Bus Cycles

18524B/O-Mar1996
Signal Descriptions
AMD~
AMD5i!J6 Processor Technical Reference Manual
logic drives KEN with the first BRDY. If system logic negates
KEN, it must return as a single transfer only the bytes speci-
fied on BE7-BEO. If system logic asserts KEN, it must ignore
BE7-BEO during all transfers of the burst and return all eight
bytes for the starting address on A3i-A3. BE7-BEO does not
change during the four transfers of the burst. (This behavior is
unlike the 486 processor, which drives BE3-BEO separately for
each transfer of a burst.) System logic must determine the suc-
cessive quadword addresses for each transfer in a burst,
depending on the starting address, as shown in Section 5-4 on
page 5-22.
During single writes, which include cache writethroughs (i-to-
8-byte transfers with CACHE negated) the processor drives the
bits of BE7-BEU to indicate which of the eight bytes on D63-DO
are valid. During writebacks (32-byte, four-transfer bursts with
CACHE asserted) the processor drives all bits of BE7-BEU Low
to indicate that all eight bytes on D63-DO are valid. Write-
backs are addressed by A3i-A3 but they are always aligned to
32-byte boundaries, so A4-A3 are always O.
TABLE 5-5. Relation Of BE7-BEO To Other Signals
Byte Enable
Effective Address Bits
1
Byte On Data Parity
Output
A2 At AO
Data Bus Bit
:BEl t
1 1
D63-D56
D7
:BE6 1
1
0
D55-D48
D6
:BE5 1 0
1
D47-D40
D5
1ffi4 1
0 0
D39-D32
D4
BID 0
1 1
D31-D24
D3
BE2 0
1 0
D23-D16 D2
:BEl 0
0 1
D15-D8 Dl
:BElJ 0
0
0
D7-DO
DO
Notes:
7.
HE7-HEO expand on the function of A2-AO by aI/owing the processor to address any or all
eight bytes addressed by A3 7 -AI
The processor differentiates special bus cycles using a combi-
nation of BE7-BEU, the cycle definition (DIC, MIIU, and W/R)
outputs, and A3i-A3. The values on the cycle definition signals
are the same for all special cycles; only BE7-BEU and A3i-A3
differentiate among those cycles. Table 5-6 shows the relation-
5-15