AMD AMD5K86 - FIGURE 5-3. Single-Transfer Memory Write Delayed by

18524B/O- Mar1996
Single-Transfer
Memory Write
Delayed by EWBE
Signal
Bus Cycle Timing
AMDl'
AMD5~6 Processor Technical Reference Manual
Figure 5-3 shows two consecutive memory writes. The first
write fills an external write buffer and the second write is
stalled for three clocks by the negation of EWER.
For writes, system logic can store the address and data in a
write buffer, return BRDY, and perform the store to memory
later. If the number of outstanding writes exceeds the size of
the write buffer, system logic must negate EWER to prevent
the processor from sending additional writes until EWER is
asserted. The advantage of negating EWER as opposed to not
asserting BRDY is that negating EWER prevents only write
requests, but not asserting BRDY stalls the bus and prevents
all requests.
More specifically, if EWER is negated with or after the last
BRDY of a write cycle, the processor will not do any of the fol-
lowing:
• Write a store-buffer entry to the data cache
• Write to memory (single-transfer or burst), including locked
write to Accessed (A) bit after TLB load
• Write to 110 (OUTx)
•
Execute the following instructions:
MOVto CRO
MOV to CR4, including during a task switch
WBINVD
INVLPG
CPUID
• Respond to the following instructions:
FLUSH
sm
• Respond to any other interrupts or exceptions that cause a
write to memory, such as pushing state onto the stack or set-
ting the Accessed bit in a segment descriptor. This may
include the BUSCHK, NMI, and INTR interrupts.
For more details, see the description of EWBE on page 5-63.
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