AMD AMD5K86 - Power Saving Features; STPCLK in Halt State; Simultaneous I;O SMI Trap and Debug Breakpoint Trap

AMD~
AMD51J6 Processor Technical Reference Manual
18524B/O-Mar1996
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Power Saving Features
5TPCLK in Halt State
When in the Halt state, the AMD5
K
86 processor responds to
S'fPCLK and enters the Stop Grant state. The Pentium proces-
sor ignores STPCLK in the Halt state.
5TPCLK Pulse does not Guarantee That One Instruction
Executes
Unlike the Pentium processor, the AMD5
K
86 processor does
not guarantee that at least one instruction will be executed
between the deassertion of StPCLK and a subsequent reasser-
tion of stPCLK. On the Pentium processor, at least one
instruction is guaranteed to execute.
Simultaneous 1/0 SMI Trap and Debug Breakpoint Trap
On a simultaneous 110 SM! trap and debug breakpoint trap, the
AMD5
K
86 processor responds to the SMI first and postpones
writing the fault frame for the debug trap to the stack until
after the resumption of normal execution via RSM. (If debug
registers DR3-DRO are going to be used while in SMM, they
must be saved and restored by the SMM software. DR6 and
DR7 are automatically saved and restored.) This is similar to
the Pentium processor behavior (P54C only) with TR12.ITR set
to 1, although the postponing of the debug trap is only accom-
plished with trapped 110 instructions, where the timing of the
SM! met the requirements for SMI I/O trapping.
On the AMD5
K
86 processor, if, on the RSM, the 110 Restart
Flag in the SMM save area is set, the debug trap is cancelled
and will be redetected as a result of the reexecution of the 110
instruction.
SMM Save Area
The contents of any reserved locations are not necessarily the
same between the AMD5
K
86, Pentium, and the 486 processors.