AMD AMD5K86 - FIGURE 6-3. BOFF Example

1 8524B/O-Marl996
BOFF Arbitration
Cache
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AMD5,!J6 Processor Technical Reference Manual
cycles is of paramount importance. Support for BUFF is usu-
ally needed to resolve potential deadlock problems that arise
as a result of inquire cycles, and if BUFF is supported, there is
usually no reason to support HOLD. The sections that follow
further describe these relative advantages and disadvantages.
BUFF obtains control of the full bus (address and data) in the
next clock, intervening in any in-progress bus cycle if neces-
sary. It provides the fastest response of the three bus-hold
inputs. The processor floats its outputs in the next clock after
the assertion of BUFF. Thus, the signal can also be used not
only for inquire cycles but also to resolve deadlock between
two bus masters during inquire cycles.
BUFF is useful, and often necessary, in both single-bus and
multiple-bus systems. Because of its ability to help resolve
deadlock during shared-memory accesses to cached locations,
it is required in virtually all systems with multiple caching
masters. For example, if Master A controls the bus and
attempts to write a memory location that is cached by Master B
in a modified state, a shared L2 controller could drive an
inquire cycle to Master B, forcing a writeback. But Master B
cannot write back until Master A is off the bus. In this case, the
L2 controller could use IIITM from Master B to gate the asser-
tion of BUFF to Master A.
System logic typically drives separate BUFF signals to each
bus master in the system. The assertion by system logic of
BUFF to a shared L2 cache for an inquire cycle need not inter-
fere with the processor's continued operation out of its Ll
cache. In addition, the assertion by system logic of BUFF to a
look-through L2 cache for an inquire cycle need not interfere
with the processor's continued accesses to that L2 cache.
Figure 6-3 shows an example of BUFF in a system with two
caching masters-a processor and another caching master-
sharing the processor bus. A typical sequence for inquire
cycles that hit a modified line in the processor's cache might be
as follows:
1. The other master (or system logic) asserts BUFF to the pro-
cessor.
2. The other master (or system logic) drives an inquire cycle
(represented by £ADS) to the processor.
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