AMD AMD5K86 - AHOLD Arbitration

AMD~
AMD5~6 Processor Technical Reference Manual 18524B/O-Mar1996
AMDS
K
86
Processor
~').
V
3. The processor responds with JIITl\iI to system logic.
4. System logic asserts BUFF to the requesting master. (JIITl\iI
from the processor can be used to generate BUFF.)
5. The other master negates BUFF to the processor so that the
processor can write back its modified line to main memory
and the shared L2 cache.
(j)1lOFF
Other
G)E7iD5
Caching
Master
""\
(DHITM
• 0
(Vwriteback
@1lOFF
Processor Bus
"-
V
)
V
Look-Aside System
Main
UCache
Logic
Memory
~
System Bus
FIGURE 6-3. DOFF Example
6-16
A configuration in which both caching masters were on oppo-
site sides of a shared L2 look-through cache would have some-
what similar operations, except that the L2 cache controller
would do much of the signalling ascribed to system logic in Fig-
ure 6-3.
System Design