AMD AMD5K86 - Stop Grant State

AMD~
18524BjO-Mar1996 AMD5~6 Processor Technical Reference Manual
6.4.3 Stop Grant State
6.4.4
Clock Control
The assertion of STPCLK causes the processor to enter the
Stop Grant state. The processor can enter the Stop Grant state
from the normal operating modes (Real, Protected, or Virtual-
8086), SMM, or the Halt state.
When STPCLK is negated, the processor returns to the mode
from which it entered. If the processor entered the Stop Grant
state from the Halt state, negation of STPCLK returns the pro-
cessor to the Halt state. Otherwise, negation of STPCLK or
assertion of RESET returns the processor to the normal operat-
ing mode or SMM, from which it entered. If INIT is asserted in
the Stop Grant state, the signal is latched and acted upon after
STPCLK is negated. No processor registers are saved before
entering the Stop Grant state because the processor returns to
the next unexecuted instruction in program order when it
returns to its prior operating mode.
Within the Stop Grant state (as in the Halt state) the majority
of the processor's internal clock distribution and all internal
pullup resistors are disabled. However, its phase-lock loop still
runs, its key internal logic is still clocked, most of its inputs
and outputs retain their last state (except D63-DO and DP7-
DPO which are floated), and it still responds to input signals.
Stop Grant Inquire State
An inquire cycle driven while the processor is in the Halt or
Stop Grant state causes the processor to transition to the Stop
Grant Inquire state. As for inquire cycles driven from any
other state, system logic must assert AHOLD, BUFF, or HOLD
to obtain the address bus before driving EADS, INV, and the
inquire address.
The processor responds normally to an inquire cycle by driving
HITlVI and/or HIT and performing any necessary cache-state
transition. If HITlVI is asserted, the processor drives a normal
writeback (immediately if AHOLD is asserted, or delayed if
BUFF or HLDA is asserted) and returns to the state from which
it entered the Stop Grant Inquire state in the clock in which it
negates HITlVI. If HITlVI is not asserted, the processor returns
from the Stop Grant Inquire state to the state from which it
entered, two clocks after EADS.
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