AMD AMD5K86 - PCHK (Parity Status)

18524B/0- Mar1996
Signal Descriptions
AMD~
AMD5~6 Processor Technical Reference Manual
• In Real mode, or in Protected and Virtual-8086 modes while
paging is disabled (PG bit in CRO cleared to 0):
PCD output = CD bit in CRO
(Thus, whenever the CD bit in CRO is set to 1, the PCD out-
put is asserted and the access is non-cacheable.)
• In Protected and Virtual-8086 modes while caching is
enabled (CD bit in CRO cleared to 0) and paging is enabled
(PG bit in CRO set to 1):
For accesses to I/O space, page directory entries, and other
non-paged accesses:
PCD output = PCD bit in CR3
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PCD output = PCD bit in page directory entry
For accesses to a 4-Kbyte pages:
PCD output = PCD bit in page table entry
The method of selecting the PCD bit is similar to that for the
PWT bit, described on page 5-106. The cache disable (CD) and
not-writethrough (NW) bits in CRO are cleared to 0 for normal,
cache able operation. If a location is already cached before the
operating system sets a PCD bit to 1, any access to that location
will hit in the cache regardless of the state of the PCD bit or
signal.
CACHE is partially determined by the PCD bit. Thus, the
states of CACHE and PCD are very often the same. CACHE is
never asserted when PCD is asserted. PCD indicates the cache-
ability of an entire page, and CACHE indicates the burstability
of a particular bus cycle; burst ability is a necessary but insuffi-
cient condition for determining cacheability. The cacheability
of a particular bus cycle is determined during read cycles when
system logic asserts KEN while the processor asserts CACHE.
KEN not a factor in determining the state of the PCD or
CACHE signals. The processor drives both PCD and 7"C"A"C""Hr'TE ....
before it knows the state of KEN. For details, see the descrip-
tions of CACHE and KEN on pages 5-50 and 5-90.
5-101