AMD AMD5K86 - TABLE 3-7. Machine-Check Type Register (MCTR) Fields; Time Stamp Counter (TSC)

AMD~
AMD51J6 Processor Technical Reference Manual
18524B/O-Mar1996
].2.2
Machine-Check Type Register (MCTR)
31
Reserved
Locked Cycle
Memory or I/O Cycle
Data or Code Cycle
Write or Read Cycle
Valid Machine-Check Data
The processor latches the cycle definition and other informa-
tion about the current bus cycle in its 64-bit Machine-Check
Type Register (MCAR) at the same times that the Machine-
Check Address Register (MCAR) latches the cycle address:
when a bus-cycle error occurs. These errors are indicated
either by (a) system logic asserting BUSCHK, or (b) the proces-
sor asserting PCHK while system logic asserts PEN.
The MCTR can be read with the RDMSR instruction when the
ECX register contains the value 01h. Figure 3-9 and Table 3-7
show
the formats of the MCTR register. The contents of the
register can be read with the RDMSR instruction. The proces-
sor clears the CHK bit (bit 0) in MCTR when the register is
read with the RDMSR instruction.
If system software has set the MCE bit in CR4 before the bus-
cycle
error, the processor also generates a machine-check
exception as described in Section 3.1.1 on page 3-4.
5 4 3 2 1 0
LOCK 4
MilO 3
DIC
2
--III
WjR
1
CHK
0
FIGURE 3-9. Machine-Check Type Register (MCTR)
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