AMD AMD5K86 - TRST (Test Reset)

AMD~
18524B/O-Mar1996 AMD5~6 Processor Technical Reference Manual
5.2.53 TMS (Test Mode Select)
Summary
Sampled
Details
Signal Descriptions
Input
TMS specifies the test function and sequence of test changes
for testing on the Test Access Port (TAP).
The processor samples TMS every rising TCK edge. TMS has
an internal pullup resistor.
TMS is always sampled, except while RESET or INIT is
asserted.
If TMS is asserted for five or more clocks, the TAP controller
enters its test-reset-Iogic state, regardless of the controller
state. This action is the same as that achieved by asserting
TRST.
See the IEEE Standard Test Access Port and Boundary-Scan
Architecture (IEEE
1149.1) specification for a description of
how the TAP signals and instructions are used for testing.
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