AMD AMD5K86 - Single-Transfer Memory Write Delayed by EWBE Signal

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AMD~

AMD5~6

Processor

Technical

Reference

Manual

18524BjO-Mar1996

ClK

A31-A3

ADS

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BREQ

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D/C

D63-DO

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DP7-DPO

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PCD

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PEN

PWT

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WB/WT

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Read

Write

FIGURE

5-2.

Single-Transfer

Memory

Read

and

Write

5-144

Bus

Interface

Main Page

Table of Contents3
Overview21
Features22
Internal Architecture25
FIGURE 2-1. Internal Architecture, with Pipeline Stage26
Prefetch and Predecode27
Execution Pipeline28
FIGURE 2-2. Pipeline Stage Functions29
Fetch30
Decode31
Execute32
Integer/Shift Units33
TABLE 2-1. ALU Instruction Classes33
Floating-Point Unit34
Result35
Retire36
Cache Organization and Management37
Instruction Cache38
Data Cache39
Cache Tags40
Cache-Line Fills41
Cache Coherency42
TABLE 2-2. Cache States for Read and Write Accesses43
TABLE 2-3. Cache States for Snoops, Invalidation, and Replacements44
Snooping45
TABLE 2-4. Snoop Action46
Internal Snooping46
Buffers47
Prefetch Cache48
Replacement and Invalidation Writeback Buffer49
Snoop Writeback Buffer50
Read/Write Reordering51
Paging and the Tlbs52
Software Environment and Extensions55
FIGURE 3-1. Control Register 4 (CR4)56
TABLE 3-1. Control Register 4 (CR4) Fields57
Machine-Check Exceptions58
Mbyte Pages59
FIGURE 3-2. 4-Kbyte Paging Mechanism59
FIGURE 3-3. 4-Mbyte Paging Mechanism60
TABLE 3-2. Page-Directory Entry (PDE) Fields62
Global Pages63
FIGURE 3-5. Page-Table Entry (PTE)64
TABLE 3-3. Page-Table Entry (PTE) Fields65
Virtual-8086 Mode Extensions (VME)66
Hardware Interrupts and the VIF and VIP Extensions67
FIGURE 3-6. EFLAGS Register69
TABLE 3-4. Virtual-Interrupt Additions to EFLAGS Register69
TABLE 3-5. Instructions that Modify the if or VIF Flags70
Bitmap (IRB) Extension75
FIGURE 3-7. Task State Segment (TSS)76
TABLE 3-6. Interrupt Behavior and Interrupt-Table Access77
Protected Virtual Interrupt (PVI) Extensions78
FIGURE 3-8. Machine-Check Address Register (MCAR)79
Model-Specific Registers (Msrs)79
FIGURE 3-9. Machine-Check Type Register (MCTR)80
TABLE 3-7. Machine-Check Type Register (MCTR) Fields81
Time Stamp Counter (TSC)81
Hardware Configuration Register (HWCR)82
Cpuid83
Cmpxchg8B86
MOV to and from CR487
Rdtsc88
RDMSR and WRMSR89
Illegal Instruction (Reserved Opcode)92
Performance93
Dispatch and Execution Timing97
TABLE 4-1. Integer Instructions100
Integer Dot Product Example109
TABLE 4-2. Integer Dot Product Internal Operations Timing110
TABLE 4-3. Floating-Point Instructions111
Bus Interface119
FIGURE 5-1. Signal Groups120
TABLE 5-1. Summary of Signal Characteristics120
Signal Overview120
Signal Characteristics122
Conditions for Driving and Sampling Signals126
- TABLE 5-2. Conditions for Driving and Sampling Signals127
- External Interrupts132
- TABLE 5-3. Summary of Interrupts and Exceptions135
- Bus Signal Compatibility with Pentium Processor136
- A20M (Address Bit 20 Mask)137
- A31–A3 (Address Bus)139
- TABLE 5-4. Address-Generation Sequence During Bursts140
- ADS (Address Strobe)143
- ADSC (Address Strobe Copy)146
- AHOLD (Address Hold)147
- AP (Address Parity)150
- APCHK (Address Parity Check)151
- BE7–BE0 (Byte Enables)152
- TABLE 5-5. Relation of BE7-BE0 to Other Signals153
- TABLE 5-6. Encodings for Special Bus Cycles154
- BF (Bus Frequency)155
- TABLE 5-7. Processor-To-Bus Clock Ratios155
- BOFF (Backoff)156
- TABLE 5-8. Outputs Floated When BOFF Is Asserted157
- BRDY (Burst Ready)160
- RDYC (Burst Ready)163
- BREQ (Bus Request)164
- BUSCHK (Bus Check)165
- CACHE (Cacheable Access)168
- TABLE 5-9. MESI-State Transitions for Reads170
- CLK (Bus Clock)171
- D/C (Data or Code)172
- D63–D0 (Data Bus)174
- TABLE 5-10. Relation between D63-D0, BE7-BE0, and DP7-DP0175
- DP7–DP0 (Data Parity)176
- EADS (External Address Strobe)177
- EWBE (External Write Buffer Empty)181
FERR (Floating-Point Error)183
FLUSH (Cache Flush)185
FRCMC (Functional-Redundancy Check Master/Checker)188
HIT (Inquire-Cycle Hit)190
TABLE 5-11. MESI-State Transitions for Inquire Cycles191
HITM (Inquire Cycle Hit to Modified Line)192
TABLE 5-12. Outputs Floated When HLDA Is Asserted194
HLDA (Bus-Hold Acknowledge)194
HOLD (Bus-Hold Request)196
IERR (Internal Error)198
IGNNE (Ignore Numeric Error)199
INIT (Initialization)200
INTR (Maskable Interrupt)203
TABLE 5-13. Interrupt Acknowledge Operation Definition204
INV (Invalidate Cache Line)207
KEN (External Cache Enable)208
LOCK (Bus Lock)210
M/IO (Memory or I/O)214
NA (Next Address)215
NMI (Non-Maskable Interrupt)216
PCD (Page Cache Disable)218
PCHK (Parity Status)220
PEN (Parity Enable)221
PRDY (Probe Ready)222
TABLE 5-14. PWT, Writeback/Writethrough, and MESI224
PWT (Page Writethrough)224
R/S (Run or Stop)226
RESET (Reset)228
TABLE 5-15. Register State after RESET or INIT229
TABLE 5-16. Outputs at RESET231
SCYC (Split Cycle)233
SMI (System Management Interrupt)235
SMIACT (System Management Interrupt Active)240
STPCLK (Stop Clock)241
TCK (Test Clock)246
TDI (Test Data Input)247
TDO (Test Data Output)248
TMS (Test Mode Select)249
TRST (Test Reset)250
W/R (Write or Read)251
WB/WT (Writeback or Writethrough)252
TABLE 5-17. MESI-State Transitions for Reads253
TABLE 5-18. MESI-State Transitions for Writes254
TABLE 5-19. Bus Cycle Definitions255
Bus Cycle Overview255
Addressing256
Alignment257
Bus Speed and Typical DRAM Timing258
Bus Cycle Timing259
Single-Transfer Reads and Writes260
FIGURE 5-2. Single-Transfer Memory Read and Write262
Single-Transfer Memory Write Delayed by EWBE Signal263
FIGURE 5-3. Single-Transfer Memory Write Delayed by264
FIGURE 5-4. I/O Read and Write265
TABLE 5-20. Bus-Cycle Order During Misaligned Transfers266
Single-Transfer Misaligned Memory and I/O Transfers266
FIGURE 5-5. Single-Transfer Misaligned Memory and267
Burst Cycles268
TABLE 5-21. Address-Generation Sequence During Bursts269
FIGURE 5-6. Burst Reads270
FIGURE 5-7. Burst Read (NA Sampled)271
Burst Writeback272
FIGURE 5-8. Burst Writeback Due to Cache-Line Replacement274
Bus Arbitration and Inquire Cycles275
AHOLD-Initiated Inquire Miss276
FIGURE 5-9. AHOLD-Initiated Inquire Miss277
FIGURE 5-10. AHOLD-Initiated Inquire Hit to Shared or Exclusive Line278
AHOLD-Initiated Inquire Hit to Modified Line279
FIGURE 5-11. AHOLD-Initiated Inquire Hit to Modified Line280
Bus Backoff (BOFF)281
FIGURE 5-12. Basic BOFF Operation282
BOFF-Initiated Inquire Hit to Modified Line283
FIGURE 5-13. BOFF-Initiated Inquire Hit to Modified Line284
HOLD-Initiated Inquire Hit to Shared or Exclusive Line285
FIGURE 5-14. HOLD-Initiated Inquire Hit to Shared or Exclusive Line286
FIGURE 5-15. HOLD-Initiated Inquire Hit to Modified Line287
Locked Cycles288
FIGURE 5-16. Basic Locked Operation289
TLB Miss (4-Kbyte Page)290
FIGURE 5-17. TLB Miss (4-Kbyte Page)291
Locked Operation with BOFF Intervention292
FIGURE 5-18. Locked Operation with BOFF Intervention293
TABLE 5-22. Interrupt Acknowledge Operation Definition294
TABLE 5-23. Encodings for Special Bus Cycles299
FIGURE 5-20. Basic Special Bus Cycle (Halt Cycle)300
FIGURE 5-21. Shutdown Cycle301
FIGURE 5-22. FLUSH-Acknowledge Cycle302
FIGURE 5-23. Cache-Invalidation Cycle (INVD Instruction)303
FIGURE 5-24A. Cache-Writeback and Invalidation Cycle304
FIGURE 5-24B. Cache-Writeback and Invalidation Cycle305
TABLE 5-24. Branch-Trace Message Special Bus Cycle Fields306
FIGURE 5-25. Branch-Trace Message Cycle307
Mode Transitions, Reset, and Testing308
Stop-Grant and Stop-Clock States311
Real Mode314
FIGURE 5-28. INIT-Initiated Transition from Protected Mode to Real Mode315
System Design317
Memory Map318
FIGURE 6-1. Typical Desktop-System BIOS Memory Map319
Memory-Decoder Aliasing of Boot ROM Space320
SMM Memory Space and Cacheability321
FIGURE 6-2. Default SMM Memory Map323
Cache324
L2 Cache325
Writethrough Vs. Writeback Coherency States326
Inquire Cycles328
Bus Arbitration for Inquire Cycles330
BOFF Arbitration331
FIGURE 6-3. BOFF Example332
AHOLD Arbitration333
FIGURE 6-4. AHOLD and BOFF Example334
HOLD Arbitration335
FIGURE 6-5. Write-Once Protocol337
Cache Invalidations338
System Management Mode (SMM)339
Operating Mode and Default Register Values340
TABLE 6-1. Initial State of Registers in SMM341
SMM State-Save Area341
TABLE 6-2. SMM State-Save Area Map342
SMM Revision Identifier344
Halt Restart Slot346
I/O Trap Dword347
Exceptions and Interrupts in SMM348
SMM Compatibility with Pentium Processor349
State Transitions350
FIGURE 6-6. Clock Control State Transitions352
Stop Grant State353
- Stop Clock State354
- Clock Design356
- FIGURE 6-8. CLK Delay Function357
- FIGURE 6-9. CLK Synthesizer with Output Enable358
- FIGURE 6-10. CPUCLK Clamping Circuit358
- Noise Reduction359
- Thermal Design360
- Design Support and Peripheral Products361
- Test and Debug363
- FIGURE 7-1. Hardware Configuration Register (HWCR)365
- TABLE 7-1. Hardware Configuration Register (HWCR) Fields366
- Built-In Self Test (BIST)367
- TABLE 7-2. bist Error Bit Definition in EAX Register368
- Test Access Port (TAP) bist368
- Output-Float Test369
- FIGURE 7-2. Array Access Register (AAR)370
- TABLE 7-3. Array Ids in Array Pointers371
- Array Pointer371
- FIGURE 7-3. Test Formats: Data-Cache Tags372
- Array Test Data372
- FIGURE 7-4. Test Formats: Data-Cache Data373
- FIGURE 7-5. Test Formats: Instruction-Cache Tags374
- FIGURE 7-6. Test Formats: Instruction-Cache Instructions375
- FIGURE 7-7. Test Formats: 4-Kbyte TLB376
- FIGURE 7-8. Test Formats: 4-Mbyte TLB377
- Debug Registers378
- Debug Compatibility with Pentium Processor379
- Functional-Redundancy Checking380
- Boundary-Scan Test Access Port (TAP)381
- Device Identification Register383
- Public Instructions384
- Hardware Debug Tool (HDT)385
- A.1 Bus Signals388
- A.2 Bus Interface391
- A.2.3 Bus Cycle Order of Misaligned Memory and I/O Cycles392
- Comments393
- A.3 Bus Mastering Operations (Including Snooping)394
- Comments395
- A.3.6 Write Hit to a Shared Line in the DCACHE396
- A.4 Memory Management397
- A.5 Power Saving Features398
- A.5.5 NMI Recognition During SMM399
- A.6 Exceptions400
- A.7 Debug401

AMD AMD5K86 - Single-Transfer Memory Write Delayed by EWBE Signal

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