AMD AMD5K86 - INTR (Maskable Interrupt)

AMDl1
AMD5#6 Processor Technical Reference Manual
18524B/O-Mar1996
5-84
asserted three clocks before the BRDY of that write in order to
prevent another cycle from starting.
INIT invokes the processor's built-in self test (BIST) if asserted
at the falling edge of RESET. The BIST runs a series of tests on
the internal hardware that exercise the following resources-
all cache tags (linear and physical) and cache arrays, the entry-
point and instruction-decode PLAs, and the microcode ROM.
At the end of the BIST, a value representing the result of the
tests is stored in the EAX register. Zero means passed and any
other value means failed. The processor continues with its nor-
mal boot process after the BIST completes, whether the BIST
passed or failed.
The processor recognizes BUFF, HOLD, AHOLD, and RIS while
INIT is asserted, but these signals will not intervene in the ini-
tialization process except that they will prevent the first code
fetch (jump to BIOS) after the registers are initialized.
No other exceptions or interrupts will intervene in the initial-
ization process. The first code fetch after the registers are ini-
tialized will occur before another interrupt or exception is
recognized. The processor latches the assertion of any edge-
triggered interrupt (FLUSH, SM!, INIT, NMI) while INIT is
asserted and recognizes latched interrupts in priority order
when INIT is negated. If INIT is asserted during the Stop Grant
state, the signal is held pending until after the processor exits
the Stop Grant state, at which point it is acted upon.
Bus Interface