AMD AMD5K86 - Execute

AMD~
AMDS,!J6 Processor Technical Reference Manual
18524BjO-Marl996
2.2.3 Execute
2-8
The serializing instructions include OUTx, invalidations
(INVD, WBINVD, INVLPG), interrupt returns (IRET, IRETD,
RSM), descriptor-table-register and task-register loads (LGDT,
LLDT, LIDT, LTR),
moves to control or debug registers (MOV
to CRx or DRx), model-specific register instructions (RDMSR,
WRMSR),
and CPUID. Special bus cycles and interrupt-
acknowledge operations also serialize the pipeline. INx
instructions are not executed until the stQre buffer and write-
back buffers are drained of any pending writes.
The four converters that generate fastpath or microcode ROPs
dispatch up to four ROPs in parallel per clock to the execution
unit reservation stations.
The processor has the following execution units that work in
parallel with one another:
• Two ALUs (integer, logic, and shift operations)
• One floating-point unit
• Two load/store units
• One branch unit
Each execution unit has its own FIFO reservation station with
two or four entries. ROPs are dispatched to reservation sta-
tions in program order. One ROP can be dispatched to a single
reservation station in a given clock, thus up to four reservation
stations receive an ROP each clock. ROPs are issued from a res-
ervation station to its execution unit when all operands are
available from the register file, reorder buffer, or prior execu-
tion via forwarding (including from data cache loads), and
when the execution unit has completed its prior ROP. Issue
and dispatch occur in the same clock if the operands are avail-
able and the unit is free at dispatch time.
While ROPs are issued in order to a particular execution unit,
ROPs go out of order at the point of issue because reservation
stations issue ROPs at different times relative to each other.
The use of reservation stations and out-of-order execution
reduces instruction stalls due to dependencies on execution
resources and allows a higher issue rate to be maintained. Mul-
tiple values for the same register are resolved by providing
tags for each register value (register renaming). True data
Internal Architecture