AMD AMD5K86 - Cache

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SMM
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SMM
AMD~
AMD5/36 Processor Technical Reference Manual
0003JFFF
0003JEOO
32-Kbyte
Minimum
RAM
Service Routine Entry Point
Service Routine
1------------1 0003_8000
SMM Base Address (CS)
1---------.-, 0003_0000
FIGURE 6-2. Default SMM Memory Map
Memory
System logic controls the cache ability of SMM memory with
KEN in the same way that it controls the cache ability of mem-
ory space. If SMM memory is to be non-cacheable, KEN must
be held negated from when SlVII is asserted until SMIACT is
negated. If SMM memory is to be cacheable, KEN must be
asserted for cacheable read cycles.
6-7