AMD AMD5K86 - FIGURE 3-7. Task State Segment (TSS)

18524BjO-Mar1996
Software Interrupts
and the Interrupt
Redirection Bitmap
(IRB) Extension
AMD~
AMD5~6 Processor Technical Reference Manual
In Virtual-8086 mode, software interrupts (INTn exceptions
that vector through interrupt gates) are trapped by the operat-
ing system for emulation, because they would otherwise clear
the real IF. When VME extensions are enabled, these INTn
instructions are allowed to execute normally, vectoring
directly to a Virtual-8086 service routine via the Virtual-8086
interrupt vector table (IVT) at address 0 of the task address
space. However, it may still be desirable for security or perfor-
mance reasons to intercept INTn instructions on a vector-spe-
cific basis to allow servicing by Protected-mode routines
accessed through the interrupt descriptor table (IDT). This is
accomplished by an Interrupt Redirection Bitmap (IRB) in the
TSS, which is created by the operating system in a manner sim-
ilar to the 10 Permission Bitmap (lOPB) in the TSS.
Figure 3-7 shows the format of the TSS, with the Interrupt
Redirection Bitmap near the top. The IRB contains 256 bits,
one for each possible software-interrupt vector. The most-sig-
nificant bit of the IRB is located immediately below the base of
the IOPB. This bit controls interrupt vector 255. The least-sig-
nificant bit of the IRB controls interrupt vector O.
The bits in the IRB work as follows:
• Set-If set to 1, the INTn instruction behaves as if the VME
extensions are not enabled. The interrupt vectors to a Pro-
tected-mode routine if IOPL = 3, or it causes a general-pro-
tection exception with error code zero if IOPL<3.
• Cleared-If cleared to 0, the INTn instruction vectors
directly to the corresponding Virtual-8086 service routine
via the Virtual-8086 program's IVT.
Only software interrupts can be redirected via the IRB to a
Real mode IVT -hardware interrupts cannot. Hardware inter-
rupts are asynchronous events and do not belong to any cur-
rent virtual task. The processor thus has no way of deciding
which IVT (for which Virtual-8086 program) to direct a hard-
ware interrupt to. Because of this, hardware interrupts always
require operating system intervention. The VIF and VIP bits
described on page 3-13 are provided to assist the operating sys-
tem in this intervention.
Control Register 4 (CR4) Extensions
3-21