AMD AMD5K86 - Bus Signal Compatibility with Pentium Processor

AMD~
AMD5~6 Processor Technical Reference Manual
18524BjO-Mar1996
5.1.4
cache lines back to memory, an in-progress writeback will be
aborted, but it will be restarted after BUFF is negated, and the
PLOSH operation will then continue; any writebacks that com-
pleted before BUFF was asserted are not affected.
Bus Signal Compatibility with Pentium Processor
The differences in bus signal functions between the AMD5
K
86
and Pentium processors are described in Section A.l on page
A-2.
5.2 Signal Descriptions
5-18
The following pages describe each signal in detail. The bus
cycle protocols that use these signals are described in Section
5.3 on page 5-137. Chapter 6 describes the context in which the
SMM and clock-control signals are used, and Chapter 7 does
the same for the test signals.
Bus Interface