AMD AMD5K86 - IGNNE (Ignore Numeric Error)

AMD~
AMD5Ji36 Processor Technical Reference Manual
18524BjO-Mar1996
5.2.29
Summary
Driven
Details
5-80
IERR (Internal Error)
Output
The processor drives IERR only in Functional-Redundancy
Checking mode. If the processor is the checker and it detects a
difference in signal outputs between the master and itself, it
asserts IERR. No other errors are reported with IERR.
The processor drives IERR every clock while the processor is
operating as the checker in the Functional-Redundancy Check-
ing mode. If an error is detected, IERR is asserted for one
clock, starting two clocks after the detection of the error.
IERR is only driven in Functional-Redundancy Checking mode
when the processor is the checker, including while PRDY is
asserted within this mode.
The processor enters Functional-Redundancy Checking mode
as the checker if FRCMC is asserted at RESET. In this mode,
all of the processor's output and bidirectional signals (except
IERR and TDO) are floated and tied to those of the master pro-
cessor.
Both processors execute the same instructions, and the
checker compares the state of the master's output and bidirec-
tional signals with the state that the checker itself would have
driven for the same instruction stream.
If a mismatch occurs on such a comparison, the checker asserts
IERR for one clock, two clocks after the detection of the error.
Both the master and the checker continue running the check-
ing program after an error occurs. No action other than the
assertion of IERR is taken by the processor.
No other errors are reported with IERR. Unlike the Pentium
processor, the AMD5
K
86 processor does not report parity
errors on IERR for every cache or TLB access. Instead, the
AMD5
K
86 processor fully tests cache parity during the built-in
self test (BIST), which is invoked by asserting INIT during
RESET.
Bus Interface