AMD AMD5K86 - NA (Next Address)

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AMD51fJ6 Processor Technical Reference Manual
18524BjO-Mar1996
5.2.36
Summary
MfIO (Memory or 1/0)
Output
The processor drives MIIU to indicate whether it is accessing
memory or I/O on the bus. The signal is driven at the same time
as the other two cycle definition signals, DIC and WIR. A spe-
cific encoding of DIC, MIIU, and WIR identifies one of several
special bus cycles.
Driven and Floated MIIU is driven and floated with the same timing as DIC. See the
description of DIC on page 5-54.
Details
5-96
The processor accesses I/O when it executes an I/O instruction
(any of the INx or OUTx instructions). The processor accesses
memory when it fetches instructions or executes an instruction
that loads or stores data. Accesses to memory-mapped I/O ports
appear on the bus as memory accesses.
Only data (not code) can be read or written from the I/O
address space; the cycle definition for an I/O code read (DIC =
0, MIIU = 0, WIR = 0) defines an interrupt acknowledge cycle,
and the cycle definition for an I/O code write (DIC = 0, MIIU =
0, WIR = 1) defines a special bus cycle.
The processor specifies all special bus cycles with DIC = 0,
MIIU
= 0, and WIR = 1. The cycles are then differentiated by
BE7-BEU and A31-A3.
Bus Interface