AMD AMD5K86 - TABLE 5-10. Relation between D63-D0, BE7-BE0, and DP7-DP0

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AMD5,!J6 Processor Technical Reference Manual
1 8524B/O-Marl 996
5.2.18 D63-DO (Data Bus)
Summary
Driven, Sampled, and
Floated
Details
5-56
Bidirectional
The processor drives and samples up to eight bytes on D63-DO
during memory or I/O accesses. System logic must decode the
source and destination of these transfers using the address bus
and various control signals.
As Outputs: For single-transfer writes (including cache
writethroughs), the processor drives D63-DO valid from one
clock after xu-s- until BRDY. For writebacks (the only type of
burst write), the processor drives D63-DO valid from one clock
after xu-s- until the first BRDY, and thereafter from one clock
after each BRDY until the next BRDY of the bus cycle.
The processor floats D63-DO one clock after system logic
asserts BOFF in the clock that the processor asserts HLDA.
As Inputs: While BUFF or HLDA is asserted, the processor sam-
ples D63-DO with every BRDY of the bus cycle.
D63-DO
is driven or sampled during memory cycles (including
cache writethroughs and writebacks), I/O cycles, locked cycles,
special bus cycles, and interrupt acknowledge operations in
the normal operating modes (Real, Protected, and Virtual-
8086) and in SMM, or while PRDY is asserted. While AHOLD is
asserted, D63-DO is driven or sampled only to complete a bus
cycle that had been initiated before AHOLD was asserted, or
for inquire cycle writebacks. During the Shutdown, Halt, and
Stop Grant states, D63-DO is driven only for inquire cycle
writebacks. D63-DO is not driven or sampled during the Stop
Clock state, or while BUFF, HLDA, RESET, or INIT is asserted.
Data is transferred between the processor and memory or I/O
on up to eight bytes of the D63-DO data bus. The BE7-BEU
byte-enable signals specify the validity of each byte on D63-
DO. Table 5-10 shows the relation between D63-DO and BE7-
BEU. System logic must interpret BE7-BEU for data byte vali-
dation during single-transfer memory reads and writes and for
all I/O reads and writes. However, for burst reads (cache line
fills) and writes (cache writebacks)-that is, when the proces-
sor asserts CACHE-the processor expects data to be valid
and will drive valid data on all eight bytes of the data bus with-
out regard to the state of BE7-BEU.
Bus Interface