AMD AMD5K86 - FIGURE 5-24 A. Cache-Writeback and Invalidation Cycle

18524B/O-Mar1996
Cache-Invalidation
Cycle (INVD
Instruction)
AMD~
AMD5J1l6 Processor Technical Reference Manual
Figure 5-23 shows the cache-invalidation special bus cycle,
which the processor drives in response to the execution of the
INVD instruction. The INVD instruction causes the processor
to invalidate each line in its instruction and data caches. Modi-
fied lines in the data cache are not written back.
Although the execution of INVD is not visible on the bus, the
lack of activity on the bus as the microcode invalidates the
lines in the internal cache can be seen. When all lines in both
caches are invalidated, the processor drives the cache-invalida-
tion special bus cycle (BE7-BEU = FDh). System logic must
respond by asserting BRDY. When it does, the processor typi-
cally begins driving one or more burst reads on the bus to refill
its caches.
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, Instruction I Cache Invalidation
, Completes : Special Cycle
.
FIGURE 5-23. Cache-Invalidation Cycle (INVD Instrudion)
Bus Cycle Timing
5-185