AMD AMD5K86 - A.3.6 Write Hit to a Shared Line in the DCACHE

AMD~
18524BjO-Mar1995
AMD5J136 Processor Technical Reference Manual
Comments
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the code sequence and, therefore, unpredictable from an exter-
nal system point of view.
In treating the snoop as a hit, the AMD5
K
86 and Pentium pro-
cessors assert the HIT pin and also cache the line as either
shared or invalid, depending on the state of the INV pin. The
cycle restarts after the deassertion of BUFF and AHOLD.
In treating the snoop as a miss, the AMD5
K
86 processor deas-
serts the HIT pin. The state of the line is determined based on
KEN, WBIWT, and PWT when the cycle is restarted after the
deassertion of BUFF and AHOLD.
The behavior of snoops to the line fill buffer before cacheabil-
ity is determined is described in Section A.3.1.
Snoop Before Write Hit to ICACHE Appears on Bus
If a write to a valid ICACHE line occurs and a snoop occurs to
the same line before the write appears on the bus, the Pentium
processor generates a snoop hit until the write is on the bus.
The AMD5
K
86 processor generates a snoop miss in the window
between when the cache is invalidated and the write appears
on the bus. The ICACHE line is invalidated in both processors
by the time the write appears on the bus.
Invalidations during a FLUSH/WBINVD
During a FLUSHlWBINVD between a line copyback and the
Flush Acknowledge cycle, a subsequent snoop to that line
reports a snoop hit modified and generates another copyback.
The Pentium processor invalidates lines as they are accessed
during FLUSH. The AMD5
K
86 processor invalidates all lines at
the end of a FLOSH.
Once FLUSHlWBINVD has completed, the entire cache is
invalid for both the AMD5
K
86 and Pentium processors.
Cache Line Ownership
When the processor generates a read hit to a line in its own
ICACHE, the Pentium processor invalidates the ICACHE and
initiates a DCACHE line filL However, the AMD5
K
86 processor
Bus Mastering Operations (including Snooping)
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