AMD AMD5K86 - TABLE 5-19. Bus Cycle Definitions; Bus Cycle Overview

AMD~
AMD5i<!J6 Processor Technical Reference Manual
18524B/O-Mar1996
TABLE 5-18. MESI-State Transitions for Writes
Result of Cache Lookup
Signal or Event
Write Hit
Write Miss
exclusive
shared
or modified
CACHE, PCDI -
- -
-
-
KEN
- -
-
-
-
PWT2
-
1
-
0
-
WBIWT
- -
0 1
-
Cache Update no yes yes yes
yes
Write to Memory
write through writethrough
writethrough write through
no
(1 to 8 bytes) (1 to 8 bytes)
(1 to 8 bytes) (1 to 8 bytes)
State After Write
3
-
shared shared exclusive modified
Notes:
-
Don't care or not applicable.
7.
2.
J
5-136
The PCD bit is negated and VfCFIE is asserted during a write hit but these states do not affect the hit.
The PWT bit in the page table entry or CRJ
Transition occurs after any write to memory. Lines in shared MESI state are said to be in writethraugh state. ThfJse in exclusive or
modified MESI states are said to be in writeback state.
In single-processor systems with no other caching master, WBI
WT is typically tied High. This allows the processor to cache all
cacheable reads in the exclusive state, and all cacheable writes
update only the cache. In systems with multiple caching mas-
ters, WBIWT can be generated after inquire cycles to all other
caching masters by the logical OR of HIT from all of the mas-
ters. This allows the processor to cache reads in the exclusive or
modified state only if no other master has a copy.
While the writeback configuration usually supports higher per-
formance, the writethrough configuration is required for cer-
tain transitions in the write-once cache protocol. For details on
this protocol, see Section 6.2.6 on page 6-19.
During the Hardware Debug Tool (HDT) mode, WBIWT is only
meaningful for cache write misses (PWT = 0 and WBIWT = 1
transition a shared line to an exclusive line). The signal is not
meaningful during cache read misses in the HDT mode,
because the caches are never filled in the HDT mode.
For more details on data-cache MESI state transitions during
reads, see Table 5-9 on page 5-52 and Section 6.2.2 on page 6-9.
Bus Interface