AMD AMD5K86 - Alignment

AMD~
18524B/O-Mar1996 AMD5,!36 Processor Technical Reference Manual
5.3.3 Alignment
Bus Cycle Overview
For purposes of bus cycles, the term aligned means:
• 2- and 4-byte transfers lie within 4-byte address boundaries
• 8-byte transfers lie within 8-byte address boundaries
(For purposes of exceptions, the term aligned means situated
on the natural boundaries of an instruction or operand. Thus, a
2-byte transfer that crosses a 2-byte address boundary may
incur an alignment exception, but it will be performed as an
aligned bus cycle.)
If data on D63-DO are misaligned, the processor generates
additional bus cycles to complete the transfer. For example, if
a 4-byte transfer begins at address x07h, one byte will be trans-
ferred during the first bus cycle and the remaining three bytes
will be transferred during a second bus cycle, which will nor-
mally occur immediately after the first bus cycle (unless inter-
vened by an interrupt or bus backoff). If the misaligned
transfer is run as a locked cycle, the processor asserts both
LOCK and SCYC throughout the misaligned sequence of bus
cycles.
If memory reads, memory writes, or I/O reads are misaligned,
the AMDS
K
86 processor runs the bus cycles in the opposite
order of the Pentium processor. The AMDS
K
86 processor trans-
fers the least-significant bytes first followed by the most-signif-
icant bytes. I/O writes, however, are performed in the same
order on both processors: the most-significant bytes first, fol-
lowed by the least-significant bytes.
For a misaligned CMPXCHG8B operation (that is, the operand
does not lie on an 8-byte quadword boundary), the AMDS
K
86
processor does two split-cycle reads followed by two split-cycle
writes, all with LOCK asserted, for a total of eight bus cycles.
The Pentium processor combines the cycles for a maximum of
four bus cycles.
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