AMD AMD5K86 - IERR (Internal Error)

18524B/0- Mar1996
Signal Descriptions
AMD~
AMD5~6 Processor Technical Reference Manual
Like AHOLD but unlike BDFF, HOLD allows the processor to
complete an in-progress bus cycle before the processor floats
its cycle-driving outputs. Such an in-progress cycle may consist
of a single-transfer cycle, burst cycle, sequence of locked
cycles (such as an interrupt acknowledge operation), or a spe-
cial bus cycle. The processor supports only one in-progress bus
cycle; no pending bus cycles are buffered. Like BDFF, HOLD
has no effect on writes to the processor's store buffer, except to
delay them. (The store buffer is situated between the execu-
tion units and the data cache, and it is used for speculative
stores prior to being written in non-speculative state to the
data cache.)
When HOLD is asserted, system logic may continue asserting
HOLD for as long as it wants. The processor has no way of
breaking the hold. The processor continues driving HLDA until
two clocks after HOLD is negated, at which time the processor
may again drive its own cycles with ADS in the next clock after
it negates HLDA. During the time HOLD is asserted, the pro-
cessor attempts to operate out of its cache. If it can no longer
do so, it asserts BREQ continuously.
There are three methods by which system logic can obtain con-
trol of the address bus to drive an inquire cycle: AHOLD,
BDFF, or HOLD. AHOLD obtains control only of the address
bus and allows another master to drive only inquire cycles,
whereas BDFF and HOLD obtain control of the full bus
(address and data), allowing another master to drive not only
inquire cycles but also read and write cycles. Unlike BTIFF,
AHOLD and HOLD both permit an in-progress bus cycle to
complete, but write backs can occur while AHOLD is asserted,
whereas pending write backs during the assertion of HOLD
occur after HOLD is negated, which is similar to BUFF.
If EAIJS is asserted on the same clock that HOLD is negated,
the processor recognizes this as a valid inquire cycle and han-
dles it correctly. However, if EAIJS is asserted on the clock fol-
lowing the negation of HOLD, the AMD5
K
86 processor does not
recognize this as a valid inquire cycle.
See the description of HLDA on page 5-76 for additional
details about the HOLD/HLDA protocoL
5-79