AMD AMD5K86 - NMI (Non-Maskable Interrupt)

AMD~
185248/0- Mar1996
AMD5~6 Processor Technical Reference Manual
5.2.:57
NJ( (Next Address)
Input
Summary
Sampled
Details
Signal Descripnons
The assertion of NA indicates that external memory is pre-
pared for a pipelined cycle.
The processor samples NA from one clock after ADS until the
first expected BRDY of a bus cycle.
NA is sampled during memory cycles and writethroughs in the
normal operating modes (Real, Protected, and Virtual-808G)
and in SMM. NA is not sampled during writebacks, I/O cycles,
locked cycles, special bus cycles, or interrupt acknowledge
operations; or in the Shutdown, Halt, Stop Grant, or Stop Clock
states; or while BUFF, HLDA, RESET, INIT, or PRDYis
asserted. While AHOLD is asserted, NA is sampled only to
complete a bus cycle already begun before the assertion of
AHOLD.
NA is an input that is asserted when external memory is pre-
pared to accept a pipelined cycle. The AMD5
K
8G processor
drives the pending ADS two clocks after NA is sampled active.
NA does not generate pipelined cycles when IDCK is asserted,
during writeback cycles, or when there are no pending internal
cycles. Furthermore, locked or writeback cycles are not pipe-
lined. KEN and WBfWT are sampled when NA or BRDY is
asserted, whichever comes first.
Refer to the appropriate data sheet for model-specific details
regarding the operation of NA.
5-97