AMD AMD5K86 - Page 217

AMD~
AMD5#6 Processor Technical Reference Manual 18524BjO-Mar1996
5.2.38
Summary
Sampled
Details
5-98
NMI (Non-Maskable Interrupt)
Input
The assertion of NMI causes the processor to enter an interrupt
service routine using a predefined interrupt vector.
The processor samples NMI every clock and recognizes it at the
next instruction boundary. NMI is a rising-edge-triggered inter-
rupt and is latched when sampled. The signal must be negated
for at least four clocks before being asserted.
NMI is sampled during memory cycles (including cache
writethroughs and writebacks), cache accesses, 110 cycles,
locked cycles, special bus cycles, or interrupt acknowledge
operations in the normal operating modes (Real, Protected,
and Virtual-8086) and in SMM; in the Shutdown, Halt, or Stop
Grant states; or while AHOLD, BOFF, or HLDA is asserted.
NMI is not sampled in the Stop Clock state, or while RESET,
INIT, or PRDY is asserted.
If INIT and NMI are both asserted during the Stop Grant state
(not necessarily simultaneously), the AMD5
K
86 processor rec-
ognizes the INIT after leaving the Stop Grant state, then it rec-
ognizes the NMI prior to fetching any instructions. Current
implementations of the Pentium processor do not recognize the
NMI in such cases, although future implementations may.
NMI is
the sixth-highest-priority external interrupt. For details
on its relationship to other interrupts and exceptions, see Sec-
tion 5.1.3 on page 5-14 and Table 5-3 on page 5-17.
System logic can drive the signal either synchronously or asyn-
chronously (see the data sheet for synchronously driven setup
and hold times).
NMI is
normally used by system software to report errors such
as parity, low battery, 110 channel check, board removal, time-
out, and other system states that require operator attention. If
such an error occurs, system software can, for example, display
a screen message and wait for the operator to continue opera-
tion, if possible. In this sense, the applications for NMI are sim-
ilar to those for BOSCHK and the Shutdown state, although the
three are not functionally related. In typical PC systems, the
signal is controlled by a system software interrupt to BIOS or a
write to an 110 port (such as port 61h and/or 92h). In spite of its
Bus Interface