AMD AMD5K86 - PCD (Page Cache Disable)

18524B/O-Mar1996
Signal Descriptions
AMD~
AMD5~6 Processor Technical Reference Manual
name, some PC systems allow the interrupt to be masked with
a write to an 110 port (such as port 70h).
Upon recognizing an NMI interrupt at the next instruction
retirement boundary, the processor performs the following
actions, in the order shown:
1. Flush Pipeline-The processor invalidates all instructions
remaining in the pipeline.
2. Service Interrupt-The processor saves its state and
accesses vector 2 in the interrupt vector table (IVT) or
interrupt descriptor table (IDT), depending on whether the
processor is running in Real mode or Protected mode. The
vector identifies a gate descriptor in the table. The IDT, for
example, can contain interrupt, trap, or task gates, all of
which point indirectly to the entry point of an interrupt ser-
vice routine.
The processor recognizes BUFF, HOLD, and AHOLD while
NMI is asserted and these signals will intervene in the NMI ser-
vice routine. The processor latches the assertion of any edge-
triggered interrupt (FLUSH, sm, INIT, NMI) while BUSCHK
is asserted and recognizes latched interrupts in priority order
when BUSCHK is negated. If NMI is asserted during the Stop
Grant state, the signal is held pending until after the processor
exits the Stop Grant state, at which point it is acted upon.
During SMM, the Pentium processor does not respond to NMI
until the beginning of its response to the first INTR or software
interrupt (INTn) to occur after entering SMM. NMIs can thus
be enabled by using a dummy interrupt. When an INTR or soft-
ware interrupt is recognized, the processor first responds to a
pending NMI interrupt before executing the first instruction of
the INTR handler. By contrast, the AMD5
K
86 processor recog-
nizes a pending NMI interrupt after returning (via the IRET
instruction) from a prior interrupt.
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