AMD AMD5K86 - FIGURE 6-9. CLK Synthesizer with Output Enable; FIGURE 6-10. CPUCLK Clamping Circuit

18524B/O-Mar1996
Clock Design
AMD~
AMD5J!36 Processor Technical Reference Manual
The clock signal to the processor can be gated with one of the
following methods:
• Chipset-Figure 6-8 illustrates a delay function that gates
the system CLK with PWRGOOD to generate the CLK input
to the processor (CPUCLK) and RESET. Such a function
can easily be implemented by a chipset.
• Clock Synthesizer with Output Enable-Figure 6-9 illustrates
a clock synthesizer with an DE input driven by PWRGOOD.
• Clock Clamping Circuit-Figure 6-10 illustrates a clamping
circuit that grounds CPUCLK for a predetermined time.
The clock clamping circuit shown in Figure 6-10 has several
advantages. In addition to delaying CPUCLK until Vee has
reached specification, it also prevents noise glitches on the
clock signal from being sensed by the processor during this
time. Noise glitches are typically caused by poor design of the
clock generator startup circuit, poor layout of the PCB, power
supply ringing while Vee is reaching specification, or a long
voltage slew rate (such as 100 ms). The integrity of CPUCLK is
best maintained by passing CPUCLK directly from the core
logic.
ClK
CPUClK
Chipset
PWRGOOD
RESET
FIGURE 6-8. elK Delay Function
6-41