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AMD AMD5K86 - R;S (Run or Stop)

AMD AMD5K86
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185248/0-
Mar1996
Signal
Descriptions
AMD~
AMD5~6
Processor
Technical
Reference
Manual
the
accessed
line
is
cached
in,
transitions
to,
or
remains
in
the
shared
state
after
the
access.
If
PWT is Low
and
WBIWT
is
High,
the
accessed
line
is
cached
in,
transitions
to,
or
remains
in
the
exclusive
state
after
a
read
miss
or
the
first
write
hit.
A
subsequent
write
to
an
exclusive
line
changes
it
to
modified.
The
state
of
the
PWT
output
is
based
on
the
state
of
several
bits
written
by
the
operating
system.
In
Protected
mode,
the
PWT
output
applies
to
the
entire
current
page
rather
than
to
the
specific
bus
cycle
that
the
WBIWT
output
applies
to,
and
it
is
the
operating
system's
(rather
than
the
processor
hard-
ware's)
determination
of
writeback
or
writethrough
state.
The
bits
that
determine
the
PWT
output
are
stored
in
a proces-
sor
control
register
or
the
TLB.
Those
bits
include
the
paging
enable
(PG)
bit
in
CRO
and
the
page
writethrough
(PWT)
bit
in
one
of
three
locations.
The
selection
of
bits
depends
on
the
pro-
cessor's
operating
mode
and
the
type
of
access,
as
follows:
•
In
Real
mode,
and
in
Protected
and
Virtual-8086
modes
while
paging
is
disabled
(PG
bit
in
CRO
cleared
to
0):
PWT
output
= Low
(writeback)
•
In
Protected
and
Virtual-8086
modes
while
paging
is
enabled
(PG
bit
in
CRO
set
to
1):
For
accesses
to
I/O
space,
page
directory
entries,
and
other
non-paged
accesses:
PWT
output
=
PWT
bit
in
CR3
For
accesses
to
4-Kbyte
page
table
entries
or
4-Mbyte
pages:
PWT
output
=
PWT
bit
in
page
directory
entry
For
accesses
to
a 4-Kbyte
pages:
PWT
output
=
PWT
bit
in
page
table
entry
The
method
of
selecting
the
PWT
bit
is
similar
to
that
for
the
PCD
bit
as
described
on
page
5-100.
The
cache
disable
(CD)
and
not-write
through
(NW)
bits
in
CRO
are
cleared
to
0 for nor-
mal,
cache
able
operation.
In
the
Hardware
Debug
Tool (HDT)
mode,
PWT
is
only
mean-
ingful
for
cache
write
misses
(PWT = 0
and
WBfW'r
= 1
transi-
tion
a
shared
line
to
an
exclusive line).
The
signal
is
not
meaningful
during
cache
read
misses
in
HDT
mode,
because
the
caches
are
never
filled
during
HDT
mode.
5-107

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